1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to a method for forming a connection to a gate stack of a vertical transistor while providing protection for a gate conductor during bitline contact formation.
2. Description of the Related Art
To increase memory cell density on a surface of a semiconductor chip, vertically disposed transistors have been introduced. Processing to form these vertical devices (vertical transistors) typically includes forming a portion of a gate conductor in a trench and forming a portion of the gate conductor above the trench. The portion of the gate conductor in the trench permits conduction in a channel formed in a substrate adjacent to the gate conductor. Current flow in the channel occurs when a voltage is applied to the gate conductor.
Since the portion of the gate conductor formed outside the trench, also called a gate stack must be patterned, an etching process is employed to etch the gate stack to form a word line above the trench. Currently all processes with vertical array transistors suffer form a small gate stack etch process window.
To ensure the removal of all unwanted conductive material from a surface of a semiconductor device overetching of the gate stack materials is often employed. The overetching of gate stack layer removes all unwanted conductive materials that could cause that wordline-bitline shorts. However, since the formation of the gate stack is very sensitive to misalignment, any shift or misalignment of the gate stack relative to the trench over which the gate stack is formed exposes the gate conductor in the trench. Another problem arises if the trench is oversized as compared to the width of the gate conductor. This situation is common since process bias typically increases the trench size. This situation makes shorts between wordlines and bitlines more likely since bitline contacts, which are formed next to the gate stack, have a higher probability of making contact with the gate conductor in the trench.
The time necessary to etch the gate stack in a support area or any misalignment of the gate stack with respect to the trench over which the gate stack is formed, results in a recessed profile of the gate conductor of the vertical array device. Misalignment between the gate stack and the portion of the gate conductor formed inside the trench may cause etching of or damage to the gate conductor in the trench unless process parameters are tightly controlled.
Since it is undesirable to etch the portion of the gate conductor inside the trench when patterning the gate stack outside the trench, the process window is maintained very tightly. Tight process windows are difficult to maintain, however, and contribute to manufacturing difficulties in semiconductor fabrication.
Therefore, a need exists for a fabrication method for forming a gate conductor, which enables greater leeway in an etching process window for a gate stack patterning etch and provides increased etching time to ensure proper removal of conductive materials used in the formation of the gate stack.
A method for fabricating a gate structure deposits a first conductive material in a trench formed in a substrate and recesses the first conductive material to a level below a top surface of the substrate in the trench. A dielectric layer is conformally deposited in contact with the first conductive material in the trench and in contact with sidewalls of the trench. A hole is formed in the dielectric layer to expose the first conductive layer, and the hole is filled with a conductive material. A gate stack is formed over the trench such that an electrical connection is made to the first conductive layer in the trench by employing the conductive material through the dielectric layer.
In other methods, the step of recessing the first conductive material may include the step of providing an etch mask layer to etch a top surface of the substrate to form an upper portion of the trench which is wider than a lower portion of the trench. The step of conformally depositing a dielectric layer may include forming the dielectric layer in the upper portion of the trench. The step of forming a gate stack preferably includes depositing a layer polysilicon in contact with the conductive material and depositing an additional conductive material over the polysilicon layer. The first conductive layer and the conductive material inside the trench preferably form a gate conductor for a vertical transistor. The dielectric layer preferably includes nitride. The conductive layer and the conductive material preferably include polysilicon.
Another method for fabricating a gate structure for vertical transistors of the present invention includes providing a semiconductor substrate having a trench formed therein having a storage node formed in the trench, forming an isolation layer in the trench on top of the storage node, depositing a first conductive material in the trench over the isolation layer, recessing the first conductive material to a level below a top surface of the substrate in the trench, conformally depositing a dielectric layer in contact with the first conductive material in the trench and in contact with sidewalls of the trench, etching the dielectric layer to form a dielectric cap in the trench, the cap forming a hole to expose the first conductive layer, filling the hole with a conductive material, depositing a second conductive layer over the trench and patterning the second conductive layer over the trench to form a gate stack in electrical contact with the first conductive layer.
In other methods, the step of recessing the first conductive material may include the step of providing an etch mask layer to etch a top surface of the substrate to form an upper portion of the trench which is wider than a lower portion of the trench. The step of conformally depositing a dielectric layer may include forming the dielectric layer in the upper portion of the trench. The step of forming a gate stack preferably includes depositing a layer polysilicon in contact with the conductive material and depositing an additional conductive material over the polysilicon layer. The step of forming a gate oxide on a sidewall of the trench is preferably included. The method may include the step of performing an angled implantation of dopants to form a junction along a sidewall of the trench. The dielectric layer preferably includes nitride. The first and second conductive layers and the conductive material preferably include polysilicon.
A semiconductor device of the present invention includes a gate conductor formed in a trench, a gate stack formed over the gate conductor and a dielectric cap layer formed between the gate conductor and the gate stack. The cap layer permits an electrical connection between the gate conductor and the gate stack and prevents damage of the gate conductor during the formation of the gate stack.
In other embodiments, the cap layer preferably includes nitride. The trench is formed in a substrate, the trench including an upper portion and a lower portion, the upper portion of the trench being wider than the lower portion of the trench. The wider portion forms a recess into which the cap layer may be formed. The cap layer is preferably formed in the upper portion of the trench below a top surface of the substrate. The gate stack is preferably a word line and the gate conductor is preferably a gate for a vertical transistor.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.